The present invention relates to local interconnect structures in an integrated circuit, and methods for making the same.
A continuing trend in semiconductor technology is to build integrated circuits with more and faster semiconductor devices. The drive toward this ultra large-scale integration has resulted in a continued shrinking of device and circuit features. To take advantage of an increasing number of devices and to form the devices into one or more circuits, the various devices must be interconnected.
Ultra-large scale integrated circuit technology includes the formation of isolated semiconductor devices formed within the surface of silicon wafers and interconnecting these devices with wiring layers above the surface. The interconnection system typically consists of two or more levels of interconnection metallurgy, separated by insulation layers. The first level of interconnection is used to define small fundamental circuits, e.g., a basic CMOS inverter requiring that the gates on NMOS and PMOS devices are connected together. Memory cells such as 6T SRAM, in particular, require several such local interconnections.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semiconducting regions (e.g., active regions of one or more devices). More specifically, local interconnects are routing-restricted interconnect levels used for the short metallization runs, such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure within the integrated circuit.
Local interconnects are typically formed of low resistance material, such as a conductor or a doped semiconductor that is formed to electrically couple selected regions. A commonly used technique for forming local interconnects is the Damascene process. In this process a first metal is inlaid into a dielectric layer. This involves first depositing the dielectric layer and then polishing via chemical mechanical polishing (CMP) to make the layer planar. The structure is then patterned and etched to form recessed trenches in the dielectric layer where conductive metal lines are to be deposited. Contact to the underlying devices is made where the trenches pass over the active device regions; elsewhere the dielectric layer insulates the metal from the substrate. Generally, a sandwich structure of titanium (Ti), titanium nitride (TiN), and tungsten is next deposited in the trench and onto the dielectric surface. A second CMP is then used to remove the conductive materials from the dielectric surface, leaving metal in the trench. The CMP step is followed by a next level of interlevel dielectric (ILD) deposition, contact patterning and etching, and a filling with a conductive metal. Due to time and associated costs, it is undesirable to require two CMP processes to form a local interconnect structure.
Other methods for forming local interconnects have been used in effort to avoid the multiple CMP processing steps required by the Damascene technique. Such methods use a polycrystalline silicon (polysilicon) layer as a silicon source layer. Typically, titanium (or titanium nitride, TixNy, wherein y is less than about 0.12) is deposited over a device. Polysilicon is then deposited as a uniform layer over the titanium. An interconnect pattern is formed thereon and portions of the polysilicon layer are removed. The device is then annealed so that the titanium in contact with the polysilicon forms a titanium silicide. The remaining titanium (that did not react with the polysilicon) is removed. Theoretically, this process allows formation of self-aligned local interconnects. In practice, however, titanium that does not overly the polysilicon source layer nonetheless typically leaches silicon (i.e., reacts with free silicon) from those portions of the polysilicon source layer that are adjacent the titanium resulting in the formation of stringers. Stringers cause electrical shorting between devices.
To overcome the deficiencies in the prior art, the present invention provides local interconnect structures that are free of stringers. The present invention also provides methods for making such local interconnect structures wherein the methods do not require two or more CMP processing steps. Because local interconnect structures form electrical connections of relatively short distances (typically about 0.5 xcexcm to about 10 xcexcm), the material forming the local interconnects need not possess a low resistance value (as compared to materials forming electrical interconnections of greater distances (i.e., typically distances greater than 10 xcexcm)). Accordingly, materials other than polycrystalline silicon are used in the present invention to form a silicon source layer for fabrication of local interconnect structures.
The present invention provides methods for forming a local interconnect structures for integrated circuits. In a representative method, a substrate having a surface and including at least one topographical structure thereon (such that a region of the surface of the substrate is exposed) is provided. An active area is preferably formed in the substrate prior to formation of the topographical structure. A thin silicon source layer is then deposited over at least a portion of the active area. The silicon source layer preferably comprises silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (as occurs with the use of polysilicon). A silicide forming material, such as a refractory metal, is deposited directly upon selected regions of the silicon source layer and over the topographical structure. The structure is then preferably annealed to form a suicide layer from the refractory metal and silicon source layer. The silicide layer creates a portion of the local interconnect structure. Remaining non-reacted suicide forming material (e.g., regions of the silicon source layer not in direct, intimate contact with the silicide forming material) is removed and an interlevel dielectric is deposited over the silicide layer. The interlevel dielectric includes at least one recess defined substantially over the active area. An electrically conductive material is deposited in the recess to complete the local interconnect structure.
According to another representative embodiment a method of forming a local interconnect structure for an integrated circuit is provided wherein a silicide forming material, e.g., a refractory metal, is deposited prior to deposition of a silicon source layer. The silicon source layer preferably comprises silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers. The silicon source layer is deposited over the refractory metal and is patterned and etched to form a hard mask. The remainder of the method is essentially identical to the representative embodiment set forth above.
According to another aspect of the present invention, local interconnect structures are provided. A representative embodiment of the local interconnect structure preferably includes a substrate having at least one topographical structure, such as a gate stack. At least one active area is adjacent to the topographical structure. Silicon source overlays a portion of the substrate and a portion of the topographical structure. A silicide layer covers at least a portion of the active area and extends over a portion of the topographical structure thereby forming a portion of the local interconnect structure. An oxide layer preferably overlays the silicon source but not the silicide layer. A passivation layer covers the oxide layer and the silicide layer. The passivation layer includes at least one recess that extends through the passivation layer and terminates substantially at the active area. An electrically conductive material substantially fills the recess to form an electrical contact with the silicide layer and the active area.